Integrated clock generators for any SmartNIC design

Adoption of 56G and 112G SerDes in data center switch SoC platforms are enabling significant increases in bandwidth, however as these data rates and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get cut in half, presenting new design challenges. We offer the largest portfolio of timing products for 100G/400G switch platforms, addressing both synchronous and asynchronous architectures with our sub-100 fs families of Si54x oscillators, Si5391 clock generator, Si5395/4/2 jitter attenuators, and IEEE 1588 networking synchronizer hardware and software solutions.