Timing 201 #6: The Case of the Autonomously Resetting Clock Generator

Timing 201 #6: The Case of the Autonomously Resetting Clock Generator

Author: Kevin G. Smith

Introduction

Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up.  We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. 

Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab.
This enabled us to more quickly determine the root cause and verify the solution.

It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.

BLUF (Bottom Line Up Front)

The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.    

Browsing the Power Supply Voltages

The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator.  I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom.

The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up.  The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold. 

What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.

I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.

Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.

An Informative Vendor Data Sheet

The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 µF tantalum.  Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation.

Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.

Demonstrating the Fix

We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.

The hack was ugly but effective:

As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks.  This outcome was good enough for the customer to take over and do additional verification testing for their particular application.

Some Lessons Learned

This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.
 

1. If you have a significantly puzzling problem, and can ship us a failing PC board, that can greatly speed up the overall debug process. I realize that may not always be possible due to availability, expense, intellectual property, or power/control issues. Reducing a failing board down to the lowest populated version may help mitigate some of these concerns.
2. When troubleshooting any functional device issue, it’s always worth double-checking the supply voltages. Regulator instabilities, more subtle than this case, may even show up as increased output clock phase noise or spurs.
3. Be aware that relatively older LDO regulators may have been designed for and require higher ESR caps than relatively newer LDO regulators.The particular vendor used by this customer sells LDO regulators of both varieties, i.e. those that require 1 Ω ESR output stability caps and those that do not.
4. Finally, it’s a good idea to make sure that schematics and BOMs call out exactly what LDO output capacitor is needed so that no one accidentally orders and installs the wrong type.

Conclusion

I hope you have enjoyed this Timing 201 article.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@skyworksinc.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

[Note: This blog article was originally posted online in June 2020. It has been lightly edited, and updated to reflect Skyworks Solutions’ acquisition of Silicon Labs’ Infrastructure and Automotive business, completed on July 26, 2021.]

Timing

By Kevin G. Smith Sr. Principal Applications Engineer